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| rev 1.1.7 5/31/01 characteristics subject to change without notice. 1 of 24 www.xicor.com preliminary information 16k (2k x 8) 2-wire rtc real time clock/calendar/alarms/cpu supervisor with eeprom features selectable watchdog timer (0.25s, 0.75s, 1.75s, off) power on reset (250ms) programmable low voltage reset 2 polled alarms settable on the second, minutes, hour, day, month, or day of the week 2-wire interface interoperable with i 2 c 400khz data transfer rate secondary power supply input with internal switch-over circuitry 2kbytes of eeprom 64-byte page write mode 3-bit block lock protection low power cmos <1? operating current <3ma active current?eprom program <400? active current?eprom read single byte write capability typical nonvolatile write cycle time: 5ms high reliability small package options 8-lead soic package, 8-lead tssop package description the x1242 is a real time clock with calendar/cpu supervisor circuits and two polled alarms. the dual port clock and alarm registers allow the clock to operate, without loss of accuracy, even during read and write operations. the clock/calendar provides functionality that is con- trollable and readable through a set of registers. the clock, using a low cost 32.768khz crystal input, accu- rately tracks the time in seconds, minutes, hours, date, day, month and years. it has leap year correction and automatic adjustment for months with less than 31 days. the x1242 provides a watchdog timer with 3 selectable time out periods and off. the watchdog activates a reset pin when it expires. the reset also goes active when v cc drops below a ?ed trip point. there are two alarms where a match is monitored by polling status bits. the device offers a backup power input pin. this v back pin allows the device to be backed up by a non- rechargeable battery. the rtc is fully operational from 1.8 to 5.5 volts. the x1242 provides a 2kbyte eeprom array, giving a safe, secure memory for critical user and con?uration data. this memory is unaffected by complete failure of the main and backup supplies. block diagram x1 x2 oscillator frequency timer logic divider calendar 8 32.768khz control/ registers 1hz time keeping registers alarm regs compare mask reset control decode logic alarm (eeprom) (eeprom) scl sda serial interface decoder 16k (2k x 8) eeprom array watchdog timer low voltage reset registers status (sram) (sram) x1242
x1242 ?preliminary information characteristics subject to change without notice. 2 of 24 rev 1.1.7 5/31/01 www.xicor.com pin configuration pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. the input buffer on this pin is always active (not gated). serial data (sda) sda is a bidirectional pin used to transfer data into and out of the device. it has an open drain output and may be wire ored with other open drain or open collector outputs. the input buffer is always active (not gated). an open drain output requires the use of a pull-up resistor. the output circuitry controls the fall time of the output signal with the use of a slope controlled pull- down. the circuit is designed for 400khz 2-wire inter- face speeds. v back this input provides a backup supply voltage to the device. v back supplies power to the device in the event the v cc supply fails. reset output?eset this is a reset signal output. this signal noti?s a host processor that the watchdog time period has expired or that the voltage has dropped below a ?ed v trip threshold. it is an open drain active low output. x1, x2 the x1 and x2 pins are the input and output, respectively, of an inverting ampli?r that can be con- ?ured for use as an on-chip oscillator. a 32.768khz quartz cr ystal is used. recommended crystal is a citizen cfs-206. the crystal supplies a timebase for a clock/ oscillator. the internal clock can be driven by an e xternal signal on x1, with x2 left unconnected. figure 1. recommended crystal connection power control operation the power control circuit accepts a v cc and a v back input. the power control circuit will switch to v back when v cc < v back ?0.2v. it will switch back to v cc when v cc exceeds v back . figure 2. power control real time clock operation the real time clock (rtc) uses an external, 32.768khz quartz crystal to maintain an accurate inter- nal representation of the year, month, day, date, hour, minute, and seconds. the rtc has leap-year correc- tion and century byte. the clock also corrects for months having fewer than 31 days and has a bit that controls 24-hour or am/pm format. when the x1242 powers up after the loss of both v cc and v back , the clock will not increment until at least one byte is written to the clock register. reading the real time clock the rtc is read by initiating a read command and specifying the address corresponding to the register of the real time clock. the rtc registers can then be read in a sequential read mode. since the clock runs continuously and a read takes a ?ite amount of time, there is the possibility that the clock could change dur- ing the course of a read operation. in this device, the x1242 x1 x2 v back v cc reset scl sda v ss 1 2 3 4 7 8 6 5 8-pin tssop x1242 x1 x2 v back v cc reset scl sda v ss 1 2 3 4 7 8 6 5 8-pin soic x1 x2 68pf 12pf 360k 10m v back v cc = v back -0.2v internal voltage v cc x1242 ?preliminary information characteristics subject to change without notice. 3 of 24 rev 1.1.7 5/31/01 www.xicor.com time is latched by the read command (falling edge of the clock on the ack bit prior to rtc data output) into a separate latch to avoid time changes during the read operation. the clock continues to run. alarms occur- ring during a read are unaffected by the read opera- tion. writing to the real time clock the time and date may be set by writing to the rtc registers. to avoid changing the current time by an uncompleted write operation, the current time value is loaded into a separate buffer at the falling edge of the clock on the ack bit before the rtc data input bytes, the clock continues to run. the new serial input data replaces the values in the buffer. this new rtc value is loaded back into the rtc register by a stop bit at the end of a valid write sequence. an invalid write operation aborts the time update procedure and the contents of the buffer are discarded. after a valid write operation the rtc will re?ct the newly loaded data beginning with the ?st ?ne second clock cycle after the stop bit. the rtc continues to update the time while an rtc register write is in progress and the rtc continues to run during any nonvolatile write sequences. a single byte may be written to the rtc without affecting the other bytes. clock/control registers (ccr) the control/clock registers are located in an area separate from the eeprom array and are only acces- sible following a slave byte of ?101111x and reads or writes to addresses [0000h:003fh]. ccr access the contents of the ccr can be modi?d by perform- ing a byte or a page write operation directly to any address in the ccr. prior to writing to the ccr (except the status register), however, the wel and rwel bits must be set using a two step process (see section ?riting to the clock/control registers. ) the ccr is divided into 5 sections. these are: 1. alarm 0 (8 bytes) 2. alarm 1 (8 bytes) 3. control (1 byte) 4. real time clock (8 bytes) 5. status (1 byte) sections 1) through 3) are nonvolatile and sections 4) and 5) are volatile. each register is read and written through buffers. the nonvolatile portion (or the counter portion of the rtc) is updated only if rwel is set and only after a valid write operation and stop bit. a sequential read or page write operation provides access to the contents of only one section of the ccr per operation. access to another section requires a new operation. continued reads or writes, once reach- ing the end of a section, will wrap around to the start of the section. a read or page write can begin at any address in the ccr. section 5) is a volatile register. it is not necessary to set the rwel bit prior to writing the status register. section 5) supports a single byte read or write only. continued reads or writes from this section terminates the operation. the state of the ccr can be read by performing a ran- dom read at any address in the ccr at any time. this returns the contents of that register location. addi- tional registers are read by performing a sequential read. the read instruction latches all clock registers into a buffer, so an update of the clock does not change the time being read. a sequential read of the ccr will not result in the output of data from the mem- ory array. at the end of a read, the master supplies a stop condition to end the operation and free the bus. after a read of the ccr, the address remains at the previous address +1 so the user can execute a current address read of the ccr and continue reading the next register. alarm registers there are two alarm registers whose contents mimic the contents of the rtc register, but add enable bits and exclude the 24-hour time selection bit. the enable bits specify which registers to use in the comparison between the alarm and real time registers. for example: the user can set the x1242 to alarm every wednes- day at 8:00am by setting the edwn, the ehrn and emnn enable bits to ? and setting the dwan, hran and mnan alarm registers to 8:00am wednesday. a daily alarm for 9:30pm results when the ehrn and emnn enable bits are set to ? and the hran and mnan registers set 9:30pm. setting the emon bit in combination with other enable bits and a speci? alarm time, the user can establish an alarm that triggers at the same time once a year. when there is a match, an alarm ?g is set. the occur- rence of an alarm can only be determined by polling the al0 and al1 bits. x1242 ?preliminary information characteristics subject to change without notice. 4 of 24 rev 1.1.7 5/31/01 www.xicor.com the alarm enable bits are located in the msb of the particular register. when all enable bits are set to ?? there are no alarms. table 1. clock/control memory map addr. type reg name bit range factory setting 76543210 (optional) 003f status sr bat al1 al0 0 0 rwel wel rtcf 01h 0037 rtc (sram) y2k 0 0 y2k21 y2k20 y2k13 0 0 y2k10 20 20h 0036 dw 0 0 0 0 0 dy2 dy1 dy0 0-6 00h 0035 yr y23 y22 y21 y20 y13 y12 y11 y10 0-99 00h 0034 mo 0 0 0 g20 g13 g12 g11 g10 1-12 00h 0033 dt 0 0 d21 d20 d13 d12 d11 d10 1-31 00h 0032 hr mil 0 h21 h20 h13 h12 h11 h10 0-23 00h 0031 mn 0 m22 m21 m20 m13 m12 m11 m10 0-59 00h 0030 sc 0 s22 s21 s20 s13 s12 s11 s10 0-59 00h 0010 control (eeprom) bl bp2 bp1 bp0 wd1 wd0 0 0 0 00h 000f alarm1 (eeprom) y2k 0 0 a1y2k21 a1y2k20 a1y2k13 0 0 a1y2k10 20 20h 000e dwa edw1 0 0 0 0 dy2 dy1 dy0 0-6 00h 000d yra unused - default = rtc year value 000c moa emo1 0 0 a1g20 a1g13 a1g12 a1g11 a1g10 1-12 00h 000b dta edt1 0 a1d21 a1d20 a1d13 a1d12 a1d11 a1d10 1-31 00h 000a hra ehr1 0 a1h21 a1h20 a1h13 a1h12 a1h11 a1h10 0-23 00h 0009 mna emn1 a1m22 a1m21 a1m20 a1m13 a1m12 a1m11 a1m10 0-59 00h 0008 sca esc1 a1s22 a1s21 a1s20 a1s13 a1s12 a1s11 a1s10 0-59 00h 0007 alarm0 (eeprom) y2k0 0 0 a0y2k21 a0y2k20 a0y2k13 0 0 a0y2k10 20 20h 0006 dwa0 edw0 0 0 0 0 dy2 dy1 dy0 0-6 0h 0005 yra0 unused - default = rtc year value 0004 moa0 emo0 0 0 a0g20 a0g13 a0g12 a0g11 a0g10 1-12 00h 0003 dta0 edt0 0 a0d21 a0d20 a0d13 a0d12 a0d11 a0d10 1-31 00h 0002 hra0 ehr0 0 a0h21 a0h20 a0h13 a0h12 a0h11 a0h10 0-23 00h 0001 mna0 emn0 a0m22 a0m21 a0m20 a0m13 a0m12 a0m11 a0m10 0-59 00h 0000 sca0 esc0 a0s22 a0s21 a0s20 a0s13 a0s12 a0s11 a0s10 0-59 00h real time clock registers year 2000 (y2k) the x1242 has a century byte that ?olls over from 19 to 20 when the years byte changes from 99 to 00. the y2k byte can contain only the values of 19 or 20. day of the week register (dw) this register provides a day of the week status and uses three bits dy2 to dy0 to represent the seven days of the week. the counter advances in the cycle 0-1-2-3-4-5-6-0-1-2-... the assignment of a numerical value to a speci? day of the week is arbitrary and may be decided by the system software designer. the clock default values de?e 0 = sunday. x1242 ?preliminary information characteristics subject to change without notice. 5 of 24 rev 1.1.7 5/31/01 www.xicor.com clock/calendar register (yr, mo, dt, hr, mn, sc) these registers depict bcd representations of the time. as such, sc (seconds) and mn (minutes) range from 00 to 59, hr (hour) is 1 to 12 with an am or pm indicator (h21 bit) or 0 to 23 (with mil = 1), dt (date) is 1 to 31, mo (month) is 1 to 12, yr (year) is 0 to 99. 24-hour time if the mil bit of the hr register is 1, the rtc uses a 24-hour format. if the mil bit is 0, the rtc uses a 12- hour format and bit h21 functions as an am/pm indi- cator with a ? representing pm. the clock defaults to standard time with h21 = 0. leap years leap years add the day february 29 and are de?ed as those years that are divisible by 4. years divisible by 100 are not leap years, unless they are also divisible by 400. this means that the year 2000 is a leap year, the year 2100 is not. the x1242 does not correct for the leap year in the year 2100. status register (sr) the status register is located in the rtc area at address 003fh. this is a volatile register only and is used to control the wel and rwel write enable latches, read two power status and two alarm bits. this register is separate from both the array and the clock/ control registers (ccr). table 2. status register (sr) bat: battery supply?olatile this bit set to ? indicates that the device is operating from v back , not v cc . it is a read only bit and is set/ reset by hardware. al1, al0: alarm bits?olatile these bits announce if either alarm 1 or alarm 2 match the real time clock. if there is a match, the respective bit is set to ?? the falling edge of the last data bit in a sr read operation resets the ?gs. note: only the al bits that are set when an sr read starts will be reset. an alarm bit that is set by an alarm occurring during an sr read operation will remain set after the read opera- tion is complete. rwel: register write enable latch?olatile this bit is a volatile latch that powers up in the low (disabled) state. the rwel bit must be set to ? prior to any writes to the clock/control registers. writes to rwel bit do not cause a nonvolatile write cycle, so the device is ready for the next operation immediately after the stop condition. a write to the ccr requires both the rwel and wel bits to be set in a speci? sequence. rwel bit is reset after each high voltage or reset by sending 00h to status register. wel: write enable latch?olatile the wel bit controls the access to the ccr and memory array during a write operation. this bit is a volatile latch that powers up in the low (disabled) state. while the wel bit is low, writes to the ccr or any array address will be ignored (no acknowledge will be issued after the data byte). the wel bit is set by writing a ? to the wel bit and zeroes to the other bits of the status register. once set, wel remains set until either reset to 0 (by writing a ? to the wel bit and zeroes to the other bits of the status register) or until the part powers up again. writes to wel bit do not cause a nonvolatile write write cycle, so the device is ready for the next operation immediately after the stop condition. rtcf: real time clock fail bit?olatile this bit is set to a ? after a total power failure. this is a read only bit that is set by hardware when the device powers up after having lost all power to the device. the bit is set regardless of whether v cc or v back is applied ?st. the loss of one or the other supplies does not result in setting the rtcf bit. the ?st valid write to the rtc (writing one byte is suf?ient) resets the rtcf bit to ?? unused bits these devices do not use bits 3 or 4, but must have a zero in these bit positions. the data byte output dur- ing a sr read will contain zeros in these bit locations. control register block protect bits?p2, bp1, bp0 (nonvolatile) the block protect bits, bp2, bp1 and bp0, determine which blocks of the array are write protected. a write to a protected block of memory is ignored. the block pro- tect bits will prevent write operations to one of eight segments of the array. the partitions are described in table 3 . addr 7 6 5 4 3 2 1 0 003fh bat al1 al0 0 0 rwel wel rtcf default 0 0 0 0 0 0 0 1 x1242 ?preliminary information characteristics subject to change without notice. 6 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 3. block protect bits watchdog timer control bits the bits wd1 and wd0 control the period of the watchdog timer. see table 4 for options. figure 4. watchdog timer time out options writing to the clock/control registers changing any of the nonvolatile bits of the clock/con- trol register requires the following steps: write a 02h to the status register to set the write enable latch (wel). this is a volatile operation, so there is no delay after the write. (operation pre- ceeded by a start and ended with a stop). write a 06h to the status register to set both the register write enable latch (rwel) and the wel bit. this is also a volatile cycle. the zeros in the data byte are required. (operation preceeded by a start and ended with a stop). write one to 8 bytes to the clock/control registers with the desired clock, alarm, or control data. this sequence starts with a start bit, requires a slave byte of ?1011110 and an address within the ccr and is terminated by a stop bit. a write to the ccr changes eeprom values so these initiate a nonvolatile write cycle and will take up to 10ms to complete. writes to unde?ed areas have no effect. the rwel bit is reset by the completion of a nonvolatile write write cycle, so the sequence must be repeated to again initiate another change to the ccr contents. if the sequence is not completed for any reason (by send- ing an incorrect number of bits or sending a start instead of a stop, for example) the rwel bit is not reset and the device remains in an active mode. see figure 13. use the following sequence. start ae ack 3f ack 02 ack stop followed by start ae ack 3f ack 06 ack stop the rwel and wel bits can be reset by writing a 0 to the status register. a read operation occurring between any of the previ- ous operations will not interrupt the register write operation. power on reset application of power to the x1242 activates a power on reset circuit that pulls the reset pin active. this signal provides several bene?s. it prevents the system microprocessor from starting to operate with insuf?ient voltage. it prevents the processor from operating prior to sta- bilization of the oscillator. it allows time for an fpga to download its con?ura- tion prior to initialization of the circuit. it prevents communication to the eeprom, greatly reducing the likelihood of data corruption on power up. when v cc exceeds the device v trip threshold value for 250ms the circuit releases reset , allowing the system to begin operation. watchdog timer operation the watchdog timer is selectable. by writing a value to wd1 and wd0, the watchdog timer can be set to 3 dif- ferent time out periods or off. when the watchdog timer is set to off, the watchdog circuit is con?ured for low power operation. watchdog timer restart the watchdog timer is restarted by a falling edge of sda when the scl line is high. this is also referred to as start condition. the restart signal restarts the watchdog timer counter, resetting the period of the counter back to the maximum. if another start fails to be detected prior to the watchdog timer expiration, then the reset pin becomes active. in the event that the restart signal occurs during a reset time out period, the restart will have no effect. bp2 bp1 bp0 protected addresses x1242 array lock 0 0 0 none none 001 600 h - 7ff h upper 1/4 010 400 h - 7ff h upper 1/2 011 000 h - 7ff h full array 100 000 h - 03f h first page 101 000 h - 07f h first 2 pgs 110 000 h - 0ff h first 4 pgs 111 000 h - 1ff h first 8 pgs wd1 wd0 watchdog time out period 0 0 1.75 seconds 0 1 750 milliseconds 1 0 250 milliseconds 1 1 disabled x1242 ?preliminary information characteristics subject to change without notice. 7 of 24 rev 1.1.7 5/31/01 www.xicor.com low voltage reset operation when a power failure occurs, and the voltage to the part drops below a ?ed v trip voltage, a reset pulse is issued to the host microcontroller. the circuitry moni- tors the v cc line with a voltage comparator which senses a preset threshold voltage. power up and power down waveforms are shown in figure 6. the low voltage reset circuit is to be designed so the reset signal is valid down to 1.0v. when the low voltage reset signal is active, the opera- tion of any in progress nonvolatile write write cycle is unaffected, allowing a nonvolatile write to continue as long as possible (down to the power on reset voltage). the low voltage reset signal, when active, terminates in progress communications to the device and pre- vents new commands, to reduce the likelihood of data corruption. figure 5. watchdog restart/time out figure 6. power on reset and low voltage reset t rsp x1242 ?preliminary information characteristics subject to change without notice. 8 of 24 rev 1.1.7 5/31/01 www.xicor.com to set the new v trip voltage, apply the desired v trip threshold voltage to the v cc pin and tie the reset pad pin to the programming voltage v p . then write data 00h to address 01h. the stop bit following a valid write operation initiates the v trip programming sequence. bring reset pad low to complete the operation. note: this operation also writes 00h to address 01h of the eeprom array. figure 7. set v trip level sequence (v cc = desired v trip value.) scl sda 01h reset v p = 15v 00h 01234567 01234567 01234567 01234567 aeh 00h resetting the v trip voltage this procedure is used to set the v trip to a ?ative voltage level. for example, if the current v trip is 4.4v and the new v trip must be 4.0v, then the v trip must be reset. when v trip is reset, the new v trip is some- thing less than 1.7v. this procedure must be used to set the voltage to a lower value. to reset the new v trip voltage, apply more than 3v to the v cc pin and tie the reset pad pin to the program- ming voltage v p . then write 00h to address 03h. the stop bit of a valid write operation initiates the v trip programming sequence. bring reset pad low to complete the operation. note: this operation also writes 00h to address 03h of the eeprom array. figure 8. reset v trip level sequence (v cc > v trip +100mv, v p = 15v) 01234567 scl sda aeh 01234567 03h reset v p = 15v 00h 01234567 01234567 00h x1242 ?preliminary information characteristics subject to change without notice. 9 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 9. sample v trip reset circuit 1 2 3 4 8 7 6 5 x1242 v trip adj . v p reset 4.7k sda scl ? adjust run 8-l soic serial communication interface conventions the device supports a bidirectional bus oriented proto- col. the protocol de?es any device that sends data onto the bus as a transmitter, and the receiving device as the receiver. the device controlling the transfer is called the master and the device being controlled is called the slave. the master always initiates data transfers, and provides the clock for both transmit and receive operations. therefore, the devices in this fam- ily operate as slaves in all applications. clock and data data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. see figure 10. figure 10. valid data changes on the sda bus scl sda data stable data change data stable start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the device continuously monitors the sda and scl lines for the start condition and will not respond to any command until this condition has been met. see figure 11. stop condition all communications must be terminated by a stop con- dition, which is a low to high transition of sda when scl is high. the stop condition is also used to place the device into the standby power mode after a read sequence. a stop condition can only be issued by the master after the slave device has released the bus. see figure 11. acknowledge acknowledge is a software convention used to indicate successful data transfer. the transmitting device, either master or slave, will release the bus after trans- mitting eight bits. during the ninth clock cycle, the receiver will pull the sda line low to acknowledge that it received the eight bits of data. refer to figure 12. x1242 ?preliminary information characteristics subject to change without notice. 10 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 11. valid start and stop conditions scl sda start stop the device will respond with an acknowledge after rec- ognition of a start condition and if the correct device identi?r and select bits are contained in the slave address byte. if a write operation is selected, the device will respond with an acknowledge after the receipt of each subsequent eight bit word. the device will acknowledge all incoming data and address bytes, except for: the slave address byte when the device identi?r and/or select bits are incorrect all data bytes of a write when the wel in the write protect register is low the 2nd data byte of a status register write oper- ation (only 1 data byte is allowed) in the read mode, the device will transmit eight bits of data, release the sda line, then monitor the line for an acknowledge. if an acknowledge is detected and no stop condition is generated by the master, the device will continue to transmit data. the device will terminate further data transmissions if an acknowledge is not detected. the master must then issue a stop condition to return the device to standby mode and place the device into a known state. figure 12. acknowledge response from receiver scl from master data output from transmitter data output from receiver 8 1 9 start acknowledge write operations byte write for a write operation, the device requires the slave address byte and the word address bytes. this gives the master access to any one of the words in the array or ccr. (note: prior to writing to the ccr, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. see ?riting to the clock/control registers on page 6.) write operation can only be done by either byte write or by page write. upon receipt of each address byte, the x1242 responds with an acknowledge. after receiving both address bytes the x1242 awaits the eight bits of data. after receiving the 8 data bits, the x1242 again responds with an acknowledge. the master then ter- minates the transfer by generating a stop condition. the x1242 then begins an internal write cycle of the data to the nonvolatile memory. during the internal write cycle, the device inputs are disabled, so the device will not respond to any requests from the master. the sda output is at high impedance. see figure 13. x1242 ?preliminary information characteristics subject to change without notice. 11 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 13. byte write sequence figure 14. writing 30 -bytes to a 64 -byte memory page starting at address 40 . s t a r t s t o p slave address word address 1 data a c k a c k a c k sda bus signals from the slave signals from the master 0 a c k word address 0 1 1 1 100000 address address 40 23 bytes 63 7 bytes address = 6 address pointer ends here addr = 7 a write to a protected block of memory is ignored, but will still receive an acknowledge. at the end of the write command, the x1242 will not initiate an internal write cycle, and will continue to ack commands. page write the x1242 has a page write operation. it is initiated in the same manner as the byte write operation; but instead of terminating the write cycle after the ?st data byte is transferred, the master can transmit up to 63 more bytes to the memory array and up to 7 more bytes to the clock/control registers. ( note: prior to writ- ing to the ccr, the master must write a 02h, then 06h to the status register in two preceding operations to enable the write operation. see ?riting to the clock/ control registers on page 6.) after the receipt of each byte, the x1242 responds with an acknowledge, and the address is internally incremented by one. when the counter reaches the end of the page, it ?olls over and goes back to the ?st address on the same page. see figure 14. this means that the master can write 64 bytes to a memory array page or 8 bytes to a ccr section starting at any location on that page. if the master begins writing at location 40 of the memory and loads 30 bytes, then the ?st 23 bytes are written to addresses 40 through 63, and the last 7 bytes are written to columns 0 through 6. afterwards, the address counter would point to location 7 on the page that was just written. if the master supplies more than the maximum bytes in a page, then the previously loaded data is over written by the new data, one byte at a time. the master terminates the data byte loading by issu- ing a stop condition, which causes the x1242 to begin the nonvolatile write cycle. as with the byte write oper- ation, all inputs are disabled until completion of the internal write cycle. refer to figure 15 for the address, acknowledge, and data transfer sequence. stops and write modes stop conditions that terminate write operations must be sent by the master after sending at least 1 full data byte and it s associated ack signal. if a stop is issued in the middle of a data byte, or before 1 full data byte + ack is sent, then the x1242 resets itself without per- forming the write. the contents of the array are not affected. x1242 ?preliminary information characteristics subject to change without notice. 12 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 15. page write sequence figure 16. current address read sequence word address 0 s t a r t s t o p slave address word address 1 data (n) a c k a c k sda bus signals from the slave signals from the master 0 data (1) (1 n 64) 1 1 1 100000 a c k a c k s t a r t s t o p slave address data a c k sda bus signals from the slave signals from the master 1 1 1 1 1 acknowledge polling disabling of the inputs during nonvolatile write cycles can be used to take advantage of the typical 5ms write cycle time. once the stop condition is issued to indi- cate the end of the master s byte load operation, the x1242 initiates the internal nonvolatile write cycle. acknowledge polling can begin immediately. to do this, the master issues a start condition followed by the slave address byte for a write or read operation. if the x1242 is still busy with the nonvolatile write cycle then no ack will be returned. when the x1242 has com- pleted the write operation, an ack is returned and the host can proceed with the read or write operation. refer to the ?w chart in figure 17. read operations there are three basic read operations: current address data read, random read, and sequential read. read operations can be done by either a byte read or a sequential read. a sequential read can be in either the ccr or eeprom array. the counter will increment after each read until the end of the address space is reached. then it will ?oll over to the start of the current address space. current address data read internally the x1242 contains an address counter that maintains the address of the last word read incre- mented by one. therefore, if the last read was to address n, the next read operation would access data from address n + 1. on power up, the sixteen bit address is initialized to 0h. in this way, a current address read immediately after the power on reset can download the entire contents of memory starting at the ?st location.upon receipt of the slave address byte with the r/w bit set to one, the x1242 issues an acknowledge, then transmits eight data bits. the mas- ter terminates the read operation by not responding with an acknowledge during the ninth clock and issu- ing a stop condition. refer to figure 16 for the address, acknowledge, and data transfer sequence. x1242 ?preliminary information characteristics subject to change without notice. 13 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 17. acknowledge polling sequence it should be noted that the ninth clock cycle of the read operation is not a ?on? care. to terminate a read operation, the master must either issue a stop condi- tion during the ninth cycle or hold sda high during the ninth clock cycle and then issue a stop condition. random read random read operations allows the master to access any location in the x1242. prior to issuing the slave address byte with the r/w bit set to one, the master must ?st perform a ?ummy write operation. the master issues the start condition and the slave address byte, receives an acknowledge, then issues the word address bytes. after acknowledging receipt of each word address byte, the master immediately issues another start condition and the slave address byte with the r/w bit set to one. this is followed by an acknowledge from the device and then by the eight bit data word. the master terminates the read operation by not responding with an acknowledge and then issu- ing a stop condition. refer to figure 18 for the address, acknowledge, and data transfer sequence. in a similar operation called ?et current address, the device sets the address if a stop is issued instead of the second start shown in figure 18. the x1242 then goes into standby mode after the stop and all bus activity will be ignored until a start is detected. this operation loads the new address into the address counter. the next current address read operation will read from the newly loaded address. this operation could be useful if the master knows the next address it needs to read, but is not ready for the data. sequential read sequential reads can be initiated as either a current address read or random address read. the ?st data byte is transmitted as with the other modes; however, the master now responds with an acknowledge, indi- cating it requires additional data. the device continues to output data for each acknowledge received. the master terminates the read operation by not responding with an acknowledge and then issuing a stop condition. ack returned? issue slave address byte (read or write) byte load completed by issuing stop. enter ack polling issue stop issue start no yes issue stop no continue normal read or write command sequence proceed yes nonvolatile write cycle complete. continue command sequence? figure 18. random address read sequence 1 slave address word address 1 a c k a c k s t a r t s t o p slave address data a c k 1 s t a r t sda bus signals from the slave signals from the master a c k word address 0 1 1 1 100000 1 1 11 x1242 ?preliminary information characteristics subject to change without notice. 14 of 24 rev 1.1.7 5/31/01 www.xicor.com the data output is sequential, with the data from address n followed by the data from address n + 1. the address counter for read operations increments through all page and column addresses, allowing the entire memory contents to be serially read during one operation. at the end of the address space the counter ?olls over to the start of the address space and the x1242 continues to output data for each acknowledge received. refer to figure 19 for the acknowledge and data transfer sequence. figure 19. sequential read sequence data (2) s t o p slave address data (n) a c k a c k sda bus signals from the slave signals from the master 1 data (n-1) a c k a c k (n is any integer greater than 1) data (1) device addressing following a start condition, the master must output a slave address byte. the ?st four bits of the slave address byte specify access to either the eeprom array or to the ccr. slave bits ?010 access the eeprom array. slave bits ?101 access the ccr. bit 3 through bit 1 of the slave byte specify the device select bits. these are set to ?11? the last bit of the slave address byte de?es the operation to be performed. when this r/w bit is a one, then a read operation is selected. a zero selects a write operation. refer to figure 19. after loading the entire slave address byte from the sda bus, the x1242 compares the device identi?r and device select bits with ?010111 or ?101111? upon a correct compare, the device outputs an acknowledge on the sda line. following the slave byte is a two byte word address. the word address is either supplied by the master device or obtained from an internal counter. on power up the internal address counter is set to address 0h, so a current address read of the eeprom array starts at address 0. when required, as part of a random read, the master must supply the 2 word address bytes as shown in figure 20. in a random read operation, the slave byte in the ?ummy write portion must match the slave byte in the ?ead section. that is if the random read is from the array the slave byte must be 1010111x in both instances. similarly, for a random read of the clock/ control registers, the slave byte must be 1101111x in both places. x1242 ?preliminary information characteristics subject to change without notice. 15 of 24 rev 1.1.7 5/31/01 www.xicor.com figure 20. slave address, word address, and data bytes (64-byte pages) slave address byte byte 0 d7 d6 d5 d2 d4 d3 d1 d0 a0 a7 a2 a4 a3 a1 data byte byte 3 a6 a5 00 0 a10 a9 a8 0 1 1 0 1 1 0 1 0 1 1 r/ w 1 device identifier array ccr 0 high order word address byte 1 low order word address byte 2 x1242 ?preliminary information characteristics subject to change without notice. 16 of 24 rev 1.1.7 5/31/01 www.xicor.com absolute maximum ratings temperature under bias .................... -65? to +135? storage temperature ...........................65? to +150? voltage on any pin (respect to ground)...............................-1.0v to 7.0v dc output current................................................ 5 ma lead temperature (soldering, 10 sec) ................300? stresses above those listed under ?bsolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device (at these or any other conditions above those indicated in the operational sections of this speci?a- tion) is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. dc operating characteristics (temperature = -40? to +85?, unless otherwise stated.) symbol parameter conditions min. typ. max. unit notes v cc main power supply 2.7 5.5 v v back backup power supply 1.8 5.5 v v cb switch to backup supply v back - 0.2 v back ?0.1 v 17 v bc switch to main supply v back v back + 0.1 v 17 i cc1 read active supply current v cc = 2.7v 400 ? 4, 5, 8, 15 v cc = 5.5v 800 ? i cc2 program supply current (nonvolatile) v cc = 2.7v 1.5 ma 4, 5, 8, 16, 17 v cc = 5.5v 3.0 ma i cc3 main timekeeping current v cc = 2.7v 2.0 ? 4, 5, 7, 16, 17 v cc =5.5v 2.5 ? i back1 backup timekeeping current v back = 1.8v 1.0 ? 4, 7, 10, 16, 17 v back = 5.5v 1.5 ? i back2 backup timekeeping current (external crystal network) v back = 1.8v 1.6 3 a 4, 7, 10, 16, 17 v back = 5.5v 7.5 15 ? i li input leakage current 10 ? 11 i lo output leakage current 10 ? 11 v il input low voltage -0.5 v cc x 0.2 or v back x 0.2 v 5, 14 v ih input high voltage v cc x 0.7 or v back x 0.7 v cc + 0.5 v back + 0.5 v 5, 14 v hys schmitt trigger input hysteresis v cc related level .05 x v cc or .05 x v back v14 v ol output low voltage v cc = 2.7v 0.4 v 12 v cc = 5.5v 0.4 v oh output high voltage v cc = 2.7v 1.6 v 13 v cc = 5.5v 2.4 x1242 ?preliminary information characteristics subject to change without notice. 17 of 24 rev 1.1.7 5/31/01 www.xicor.com notes: (1) the device enters the active state after any start, and remains active: for 9 clock cycles if the device select bits in the slave address byte are incorrect or until 200ns after a stop ending a read or write operation. (2) the device enters the program state 200ns after a stop ending a write operation and continues for t wc . (3) the device goes into the timekeeping state 200ns after any stop, except those that initiate a nonvolatile write write cycle; t wc after a stop that initiates a nonvolatile write cycle; or 9 clock cycles after any start that is not followed by the correct device s elect bits in the slave address byte. (4) for reference only and not tested. (5) v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz, sda = open (6) v il = v cc x 0.1, v ih = v cc x 0.9, f scl = 400khz, f sda = 400khz, v cc = 1.22 x v cc min (7) v cc = 0v. (8) v back = 0v. (9) v sda = v scl = v cc , others = gnd or v cc (10) v sda = v scl = v back , others = gnd or v back (11) v sda = gnd to v cc, v clk = gnd or v cc (12) i ol = 3.0ma at 5v, 1.5ma at 2.7v (13) i oh = -1.0ma at 5v, -0.4ma at 2.7v (14)threshold voltages based on the higher of v cc or v back . (15)driven by external 32.748hz square wave oscillator on x1, x2 open. (16)using recommended crystal and oscillator network applied to x1 and x2 (25?). (17)periodically sampled and not 100% tested. capacitance t a = 25 c, f = 1.0 mhz, v cc = 5v note: (1) this parameter is not 100% tested. symbol parameter max. unit test conditions c out (1) output capacitance (sda, reset ) 8 pf v out = 0v c in (1) input capacitance (scl) 6 pf v in = 0v ac characteristics ac test conditions equivalent ac output load circuit for v cc = 5v (standard output load for testing the device with v cc = 5.0v) input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10ns input and output timing levels v cc x 0.5 output load standard output load sda 1533 ? 100pf 5.0v for v ol = 0.4v and i ol = 3 ma x1242 ?preliminary information characteristics subject to change without notice. 18 of 24 rev 1.1.7 5/31/01 www.xicor.com ac specifications (t a = -40 c to +85 c, v cc = +2.7v to +3.6v, unless otherwise speci?d.) notes: (1) typical values are for t a = 25? and v cc = 5.0v (2) this parameter is not 100% tested. (3) cb = total capacitance of one bus line in pf. timing diagrams bus timing symbol parameter min. max. unit f scl scl clock frequency 0 400 khz t in pulse width suppression time at inputs 50 ns t aa scl low to sda data out valid 0.1 0.9 ? t buf time the bus must be free before a new transmission can start 1.3 ? t low clock low time 1.3 ? t high clock high time 0.6 ? t su:sta start condition setup time 0.6 ? t hd:sta start condition hold time 0.6 ? t su:dat data in setup time 100 ns t hd:dat data in hold time 0 s t su:sto stop condition setup time 0.6 ? t dh data output hold time 50 ns t r sda and scl rise time 20 + .1cb (3) 300 ns t f sda and scl fall time 20 + .1cb (3) 300 ns cb capacitive load for each bus line 400 pf t su:sto t dh t high t su:sta t hd:sta t hd:dat t su:dat scl sda in sda out t f t low t buf t aa t r x1242 ?preliminary information characteristics subject to change without notice. 19 of 24 rev 1.1.7 5/31/01 www.xicor.com write cycle timing power up timing notes: (1) delays are measured from the time v cc is stable until the speci?d operation can be initiated. these parameters are not 100% tested. (2) typical values are for t a = 25? and v cc = 5.0v nonvolatile write cycle timing notes: (1) t wc is the time from a valid stop condition at the end of a write sequence to the end of the self-timed internal nonvolatile write cycle. it is the minimum cycle time to be allowed for any nonvolatile write by the user, unless acknowledge polling is used. watchdog timer/low voltage reset operating characteristics symbol parameter min. typ. (2) max. unit t pur (1) time from power up to read 1 ms t puw (1) time from power up to write 5 ms symbol parameter min. typ. (1) max. unit t wc (1) write cycle time 5 10 ms symbol parameter min. typ. max. unit v ptrip pre-programmed reset trip voltage x1242-4.5a x1242 x1242-2.7a x1242-2.7 4.49 4.25 2.76 2.57 4.68 4.38 2.85 2.65 4.77 4.51 2.94 2.73 v t rpd v cc detect to rst low (rst high) 500 ns t purst1 power up reset time out delay 100 200 400 ms t f v cc fall time 10 ? t r v cc rise time 10 ? t wdo watchdog timer period: wd1 = 0, wd0 = 0 wd1 = 0, wd0 = 1 wd1 = 1, wd0 = 0 1.7 725 225 1.75 750 250 1.8 775 275 s ms ms t rst1 watchdog reset time out delay 225 250 275 ms t rsp 2-wire interface 1 s v rvalid reset valid v cc 1.0 v scl sda t wc 8 th bit of last byte ack stop condition start condition x1242 ?preliminary information characteristics subject to change without notice. 20 of 24 rev 1.1.7 5/31/01 www.xicor.com v trip programming timing diagram v trip programming parameters parameter description min. max. unit t vps v trip program enable voltage setup time 1 s t vph v trip program enable voltage hold time 1 s t tsu v trip setup time 1 s t thd v trip hold (stable) time 10 ms t wc v trip write cycle time 10 ms t vpo v trip program enable voltage off time (between successive adjustments) 0 s t rp v trip program recovery period (between successive adjustments) 10 ms v p programming voltage 15 18 v v tran v trip programmed voltage range 1.7 5.0 v v ta1 initial v trip program voltage accuracy (v cc applied? trip ) (programmed at 25?.) -0.1 +0.4 v v ta2 subsequent v trip program voltage accuracy [(v cc applied? ta1 )? trip . programmed at 25?.) -25 +25 mv v tr v trip program voltage repeatability (successive program operations. programmed at 25?.) -25 +25 mv v tv v trip program variation after programming (0?5?). (programmed at 25?.) -25 +25 mv v trip programming parameters are not 100% tested. v cc (v trip ) reset t tsu t thd t vph t vps v p v trip t vpo scl sda a0h 01h or 03h 00h t rp pad x1242 ?preliminary information characteristics subject to change without notice. 21 of 24 rev 1.1.7 5/31/01 www.xicor.com packaging information 0.150 (3.80) 0.158 (4.00) 0.228 (5.80) 0.244 (6.20) 0.014 (0.35) 0.019 (0.49) pin 1 pin 1 index 0.010 (0.25) 0.020 (0.50) 0.050 (1.27) 0.188 (4.78) 0.197 (5.00) 0.004 (0.19) 0.010 (0.25) 0.053 (1.35) 0.069 (1.75) (4x) 7 0.016 (0.410) 0.037 (0.937) 0.0075 (0.19) 0.010 (0.25) 0?- 8 x 45 8-lead plastic, soic, package code s8 note: all dimensions in inches (in p arentheses in millimeters) 0.250" 0.050"typical 0.050" typical 0.030" typical 8 places footprint x1242 ?preliminary information characteristics subject to change without notice. 22 of 24 rev 1.1.7 5/31/01 www.xicor.com packaging information note: all dimensions in inches (in p arentheses in millimeters) 8-lead plastic, tssop, package code v8 see detail ? .031 (.80) .041 (1.05) .169 (4.3) .177 (4.5) .252 (6.4) bsc .025 (.65) bsc .114 (2.9) .122 (3.1) .002 (.05) .006 (.15) .047 (1.20) .0075 (.19) .0118 (.30) 0??8 .010 (.25) .019 (.50) .029 (.75) gage plane seating plane detail a (20x) (4.16) (7.72) (1.78) (0.42) (0.65) all measurements are typical x1242 ?preliminary information characteristics subject to change without notice. 23 of 24 rev 1.1.7 5/31/01 www.xicor.com ordering information part mark information v cc range v trip package operating temperature range part number 16kbit eeprom 4.5 ?5.5v 4.63v ?3% 8l soic 0??0? x1242s8-4.5a -40??5? x1242s8i-4.5a 8l tssop 0??0? x1242v8-4.5a -40??5? x1242v8i-4.5a 4.5 ?5.5v 4.38v ?3% 8l soic 0??0? x1242s8 -40??5? x1242s8i 8l tssop 0??0? x1242v8 -40??5? x1242v8i 2.7 ?3.6v 2.85v ?5% 8l soic 0??0? x1242s8-2.7a -40??5? x1242s8i-2.7a 8l tssop 0??0? x1242v8-2.7a -40??5? x1242v8i-2.7a 2.7 ?3.6v 2.65v ?5% 8l soic 0??0? x1242s8-2.7 -40??5? x1242s8i-2.7 8l tssop 0??0? x1242v8-2.7 -40??5? x1242v8i-2.7 8-lead tssop eyww xxxxx 242al = 4.5 to 5.5v, 0 to +70?, v trip = 4.63v ?3% 242am = 4.5 to 5.5v, -40 to +85?, v trip = 4.63v ?3% 1242 = 4.5 to 5.5v, 0 to +70?, v trip = 4.38v ?3% 1242i = 4.5 to 5.5v, -40 to +85?, v trip = 4.38v ?3% 242an = 2.7 to 3.6v, 0 to +70?, v trip = 2.85v ?3% 242ap = 2.7 to 3.6v, -40 to +85?, v trip = 2.85v ?3% 1242f = 2.7 to 3.6v, 0 to +70?, v trip = 2.65v ?3% 1242g = 2.7 to 3.6v, -40 to +85?, v trip = 2.65v ?3% x1242 ?preliminary information characteristics subject to change without notice. 24 of 24 rev 1.1.7 5/31/01 www.xicor.com ?icor, inc. 2001 patents pending limited warranty devices sold by xicor, inc. are covered by the warranty and patent indemni?ation provisions appearing in its terms of sale onl y. xicor, inc. makes no warranty, express, statutory, implied, or by description regarding the information set forth herein or regarding the freedom of the descr ibed devices from patent infringement. xicor, inc. makes no warranty of merchantability or ?ness for any purpose. xicor, inc. reserves the right to discontinue produ ction and change speci?ations and prices at any time and without notice. xicor, inc. assumes no responsibility for the use of any circuitry other than circuitry embodied in a xicor, inc. product. no o ther circuits, patents, or licenses are implied. copyrights and trademarks xicor, inc., the xicor logo, e 2 pot, xdcp, xbga, autostore, direct write cell, concurrent read-write, pass, mps, pushpot, block lock, identiprom, e 2 key, x24c16, secureflash, and serialflash are all trademarks or registered trademarks of xicor, inc. all other brand and produc t names mentioned herein are used for identification purposes only, and are trademarks or registered trademarks of their respective holders. u.s. patents xicor products are covered by one or more of the following u.s. patents: 4,326,134; 4,393,481; 4,404,475; 4,450,402; 4,486,769; 4,488,060; 4,520,461; 4,533,846; 4,599,706; 4,617,652; 4,668,932; 4,752,912; 4,829,482; 4,874,967; 4,883,976; 4,980,859; 5,012,132; 5,003,197; 5,023,694; 5,084, 667; 5,153,880; 5,153,691; 5,161,137; 5,219,774; 5,270,927; 5,324,676; 5,434,396; 5,544,103; 5,587,573; 5,835,409; 5,977,585. foreign patents and addition al patents pending. life related policy in situations where semiconductor component failure may endanger life, system designers using this product should design the sy stem with appropriate error detection and correction, redundancy and back-up features to prevent such an occurrence. xicor s products are not authorized for use in critical components in life support devices or systems. 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) sup port or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to res ult in a signi?ant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. 8-lead soic x1242 eywwxx al = 4.5 to 5.5v, 0 to +70?, v trip = 4.63v ?3% am = 4.5 to 5.5v, -40 to +85?, v trip = 4.63v ?3% blank = 4.5 to 5.5v, 0 to +70?, v trip = 4.38v ?3% i = 4.5 to 5.5v, -40 to +85?, v trip = 4.38v ?3% an = 2.7 to 3.6v, 0 to +70?, v trip = 2.85v ?3% ap = 2.7 to 3.6v, -40 to +85?, v trip = 2.85v ?3% f = 2.7 to 3.6v, 0 to +70?, v trip = 2.65v ?3% g = 2.7 to 3.6v, -40 to +85?, v trip = 2.65v ?3% part mark information |
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